The present invention is directed, in general, to data bus architectures and, more specifically, to a space and time division multiplexing bus architecture for interconnecting a group of data transmitting devices to a group of data receiving devices.
Information systems have evolved from centralized mainframe computer systems supporting a large number of users to distributed computer systems based on local area network (LAN) architectures. As the cost-to-processing-power ratios for desktop PCs and network servers have dropped precipitously, LAN systems have proved to be highly cost effective. As a result, the number of LANs and LAN-based applications has greatly increased.
A consequential development related to the greater popularity of LANs has been the interconnection of remote LANs, computers, and other equipment into wide area networks (WANs) in order to make more resources available to users. This allows LANs to be used not only to transfer data files among processing nodes in, for example, a privately owned enterprise network, but it also allows LANs to be used to transfer voice and/or video signals in, for example, the public telephone network. However, a LAN backbone can transmit data between users at high bandwidth rates for only relatively short distances. In order to interconnect devices across large distances, different communication protocols have been developed, including X.25, ISDN, frame relay, and ATM, among others.
Most data transmissions, including file transfers and voice, occur in bursts at random intervals. The bursty nature of most data transmissions means that if the bandwidth allocated to a transmitting device is determined according to its peak demand, much bandwidth is wasted during the xe2x80x9csilencesxe2x80x9d between data bursts. This variable bandwidth demand problem has been solved in part by X.25, frame relay and ATM, which use statistical multiplexing to improve the throughput of multiple users.
In order to allow dissimilar protocol devices, such as frame relay systems and ATM systems, and different speed data lines, such as T1 and T3, to communicate with one another, a host of well-known interfaces have been developed to interconnect the dissimilar devices. For example, frame relay-to-ATM interfaces have been developed that include a high-level data link control (HDLC) interface for sending and receiving frames to and from a frame relay-based network and a segmentation and reassembly (SAR) interface for sending and receiving cells to and from an ATM-based network.
It is therefore common to find networks containing a mixture of interconnected, diverse protocol devices, such as frame relay devices and ATM devices, communicating with one another via a high-speed backbone network. To increase the effective throughput of the backbone network, it is common practice to employ access concentrators (also called xe2x80x9cconcentrators,xe2x80x9d or xe2x80x9csignal concentratorsxe2x80x9d) at or near the periphery of a network to receive lower speed data transfers from a group of devices and/or sub-networks. A concentrator allows a large number of slower speed input circuits, such as T1 lines, to be connected to a smaller number of output circuits, such as other T1 lines or high speed T3 lines, by assuming that, under ordinary circumstances, not all of the input lines transmit simultaneously (i.e., statistical multiplexing).
Many concentrators and other communications devices, such as switches, routers, bridges, etc., contain interconnection circuitry designed to direct input signals received by a group of input port devices to a group of output devices, such as protocol processors or output processors. Frequently, the internal interconnection circuitry takes the form of a communications bus that receives signals from a variable number of line interface cards (i.e., multi-source) and directs the signals to a variable number of data processing/protocol processing engines. This allows any interface card output signal to be directed to any protocol processing engine input connector (i.e., xe2x80x9cany driver to any receiverxe2x80x9d). In concentrators (or other data communication devices) where the bus speed is relatively slow, this is an adequate interconnection architecture.
However, as the speed of the bus architecture becomes greater in order to accommodate higher bandwidth data, the existence of multiple drivers on the same bus line increases problems associated with signal reflections. Each source is connected to the bus line with a discontinuity stub that causes reflections. Additionally, since all of the drivers and receivers are physically coupled together, a failure that causes any driver output or receiver input to become stuck at either a Logic 1 level or Logic 0 level will cause a failure of the entire system.
There is therefore a need in the art for an improved bus architecture for use in a communication device that performs high-speed data transfers between a group of drivers and a group of receivers. In particular, there is a need for a bus architecture capable of performing high-speed data transfers between a group of drivers and a group of receivers that is not susceptible to signal reflections associated with multiple source stubs. There is a still further need for a robust bus architecture that is not as sensitive to single point failures and which provides alternate data paths for drivers upon failure of a primary data path.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a communication device, such as an access concentrator, that performs high-speed data transfers between a group of M data drivers and a group of N data receivers, a space and time division multiplexing (STDM) bus interface in which each bus line is a single source/multidrop line that connects the output of only one driver to multiple receivers. Thus, a separate bus line is provided to each data driver to send data to any data receiver (i.e., a 1:N configuration). This minimizes the number of data reflections on each bus line by eliminating all but one of the stubs associated with the bus drivers. This also eliminates single point of failure situations, since all of the bus drivers are now spatially separated serial data streams. In a preferred embodiment of the present invention, the bus interface provides additional robustness by means of a single xe2x80x9cback-upxe2x80x9d bus line that is coupled to alternate outputs on all data drivers and to inputs on all receivers (i.e. multisource/multidrop or M:N configuration).
According to one embodiment of the present, there is provided, for use in a data communications device, a data transfer system comprising: 1) a plurality of signal source drivers capable of transmitting data streams; 2) a plurality of signal receivers capable of receiving the transmitted data streams; and 3) an interconnection bus comprising a plurality of bus lines, each of the plurality of bus lines connecting a primary output of a selected one of the signal source drivers to signal inputs on selected ones of the plurality of signal receivers.
According to another embodiment of the present invention, the data transfer system further comprises an alternate bus line connecting a secondary output on each of the plurality of signal source drivers to inputs on each of the plurality of signal receivers.
According to still another embodiment of the present invention, each of the plurality of signal source drivers normally transmits a data stream from the primary output.
According to yet another embodiment of the present invention, each of the plurality of signal source drivers transmits the data stream from the secondary output upon a failure of the primary output.
According to a further embodiment of the present invention, the selected ones of the plurality of signal receivers comprise all of the plurality of signal receivers.
According to a still further embodiment of the present invention, the data streams are time division multiplex (TDM) signals.
According to a yet further embodiment of the present invention, the data communications device comprises a concentrator capable of receiving a plurality of data signals from a plurality of external devices and each of the plurality of signal source drivers combines selected ones of the plurality of data signals to produce a combined signal having a higher bit rate than the selected data signals.
According to still another embodiment of the present invention, each of the plurality of data signals combines the selected ones of the plurality of data signals using time division multiplexing techniques.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.